The present invention relates to a semiconductor device realized by a semiconductor element, such as a MOSFET, and a method of driving the same to operate in certain manners.
A MOSFET controls electrical conduction between the source and drain by varying a voltage applied to the gate electrode. For example, in case of an N-type MOSFET, the conduction between the source and drain is allowed when a high level is inputted into the gate electrode, and stopped when a low level is inputted. Here, the potential of the well is generally fixed. More specifically, the potential is fixed at the low level in the N-type MOSFET, and the high level in a P-type MOSFET. In this manner, the conventional MOSFET is used as a 3-terminal element which controls the switching between the source and drain by using the gate electrode as an input.
FIG. 22 shows an example application of the above MOSFET by way of a circuit diagram of a logic circuit log1 as a typical conventional semiconductor device. The logic circuit log1 comprises (1) a pair of circuits of PMOSFETs (qp1 and qp2) in parallel, which are respectively provided with inputs in1 and in2 through input terminals p1 and p2, and connected to a high level VDD power source line at one end and to an output terminal p3 at the other end, and (2) a pair of circuits of NMOSFETs (qn1 and qn2) in series, which are respectively provided with the inputs in1 and in2, and connected to the output terminal p3 at one end and to a low level GND power source line at the other end, thereby forming a NAND circuit which shifts its output OUT to the high level when at least one of the inputs in1 and in2 is in the low level.
Also, FIG. 23 is a circuit diagram of a logic circuit log2 of another conventional semiconductor device. The logic circuit log2 comprises (1) a pair of circuits of PMOSFETs (qp1 and qp2) in series, which are respectively provided with the inputs in1 and in2, and connected to the high level VDD power source line at one end and to the output terminal p3 at the other end, and (2) a pair of circuits of NMOSFETs (qn1 and qn2) in parallel, which are respectively provided with the inputs in1 and in2, and connected to the output terminal p3 at one end and to the low level GND power source line at the other end, thereby forming a NOR circuit which shifts its output OUT to the low level when at least one of the inputs in1 and in2 is in the high level.
The logic circuits log1 and log2 representing the conventional semiconductor devices are arranged in such a manner that each MOSFET outputs one output in response to one input, and for this reason, the NAND circuit or NOR circuit demands four MOSFETs. Further, because an AND circuit is realized by connecting a NOT circuit (composed of two MOSFETs) to the NAND circuit in series, and an OR circuit is realized by connecting the NOT circuit to the NOR circuit in series, the AND circuit or OR circuit demands six MOSFETs. Accordingly, a large number of MOSFETs are necessary to run one operation, which makes it difficult to improve a packing density of the semiconductor device. Consequently, neither can the operating rate and yield be improved, nor the costs can be reduced.
An object of the present invention is to provide a semiconductor device capable of improving a packing density by upgrading performance of each element, and increasing an operating rate and yield, while reducing the costs, and a driving method thereof.
A first semiconductor device of the present invention is furnished with:
a semiconductor substrate;
a background insulating film formed over the semiconductor substrate;
a P- or N-type semiconductor layer which is formed over the background insulating film and made into a first electrode, the semiconductor layer in each element being separated from the semiconductor layer in an adjacent element by means of an electrical insulating separation region encircling each element;
a source region and a drain region formed in the semiconductor layer and made into a second electrode and a third electrode, respectively, the source region and drain region having a conduction type opposite to a conduction type of the semiconductor layer;
a channel region formed between the source region and drain region;
a gate insulating film formed over the channel region; and
a gate electrode formed as a fourth electrode on the gate insulating film,
wherein a contact hole is formed through the semiconductor layer for each element separated by means of the separation region, at a region other than the source region and drain region.
According to the above arrangement, by employing a substrate of an SOI (Silicon On Insulator) or SOS (Silicon On Sapphire) structure, in which elements are fabricated on the background insulating film formed over the semiconductor substrate, element forming regions for individual elements can be electrically separated from each other relatively easily by means of the separation region. Then, a MOSFET is formed in each separated element forming region under the conditions where each element is allowed to operate independently by preventing interference between the elements. Further, the semiconductor layer in each MOSFET is electrically connected to the outside through the contact hole, so that it can be used as an electrode, thereby realizing a 4-terminal element having two inputs: the input to the gate and the input to the semiconductor layer.
Consequently, a 2-input-1-output circuit can be realized by a single element, thereby upgrading the performance of the MOSFET itself. Accordingly, when a logic circuit is formed, not only can a packing density of an integrated circuit, an operating rate, and yield be improved, but also the costs can be reduced.
A second semiconductor device of the present invention is furnished with:
a semiconductor substrate;
a P- or N-type deep well region formed in the semiconductor substrate;
a shallow well region formed over the deep well region and made into a first electrode, a conduction type of the shallow well region being opposite to a conduction type of the deep well region;
a source region and a drain region formed in the shallow well region and made into a second electrode and a third electrode, respectively, the conduction type of the source region and drain region being opposite to a conduction type of the shallow well region;
a channel region formed between the source region and drain region;
a gate insulating film formed over the channel region; and
a gate electrode formed as a fourth electrode on the gate insulating film, wherein:
at least the shallow well region in each element is electrically separated from the shallow well region in an adjacent element by means of a separation region; and
a contact hole is provided to the shallow well region in each element separated from the shallow well region in the adjacent element by means of the separation region, at a region other than the source region and drain region.
According to the above arrangement, by electrically isolating the shallow well region in each element forming region by means of the separation region, a MOSFET can be formed in each separated element forming region even when a bulk substrate is employed, so that each element can operate independently by preventing interference between the elements. Further, the shallow well region in each MOSFET is electrically connected to the outside through the contact hole, so that it can be used as an electrode, thereby realizing a 4-terminal element having two inputs: the input to the gate and the input to the shallow well region.
Consequently, a 2-input-1-output circuit can be realized by a single element, thereby upgrading the performance of the MOSFET itself. Accordingly, when a logic circuit is formed, not only can a packing density of an integrated circuit, operating rate, and yield be improved, but also the costs can be saved. Moreover, the costs and resistance of the first electrode can be reduced further compared with a case where the SOI or SOS substrate is employed.
The first and second semiconductor devices are preferably arranged in such a manner that:
the elements having opposite conduction types are paired off;
a source of a P-type semiconductor element is fixed at a high potential, and a source of an N-type semiconductor element is fixed at a low potential;
gates of the P-type semiconductor element and N-type semiconductor element are connected to each other, thereby to form a first input terminal;
the contact holes in the P-type semiconductor element and N-type semiconductor element are connected to each other, thereby to form a second input terminal; and
drains of the P-type semiconductor element and N-type semiconductor element are connected to each other, thereby to form an output terminal.
In this case, the CMOS inverter structure, in which, of the two MOSFETs of P- and N-types, the source of the PMOSFET is fixed at the high potential while the source of the NMOSFET is fixed at the low potential, and the drains of the PMOSFET and NMOSFET are connected to each other, thereby to form an output, is further arranged such that the contact holes in the PMOSFET and NMOSFET are connected to each other, thereby to form the second input terminal, and the gates, namely the normal inputs, of the PMOSFET and NMOSFET are connected to each other, thereby to form the first input terminal.
Consequently, a NAND or NOR circuit can be realized by adequately adjusting potentials of the two inputs or impurity concentration in the channel region. Accordingly, the NAND or NOR circuit which conventionally demands four MOSFETs can be now realized by two MOSFETs.
Further, the first and second semiconductor devices are preferably arranged in such a manner that:
the elements having opposite conduction types are paired off;
a source of a P-type semiconductor element is fixed at a high potential, and a source of an N-type semiconductor element is fixed at a low potential;
both a gate of the P-type semiconductor element and the contact hole in the N-type semiconductor element form a first input terminal;
both a gate of the N-type semiconductor element and the contact hole in the P-type semiconductor element form a second input terminal; and
drains of both the N-type semiconductor element and P-type semiconductor element form an output terminal.
In this case, the CMOS inverter structure, in which, of a pair of a PMOSFET and an NMOSFET, the source of the PMOSFET is fixed at the high potential while the source of the NMOSFET is fixed at the low potential, and the drains of the PMOSFET and NMOSFET are connected to each other, thereby to form an output, is further arranged such that the gates of the PMOSFET and NMOSFET form the first and second input terminals, respectively, and the contact holes in the NMOSFET and PMOSFET also form the first and second input terminals, respectively.
Consequently, a NAND or NOR circuit can be realized by adequately adjusting potentials of the two inputs or impurity concentration in the channel region. Accordingly, the NAND or NOR circuit which conventionally demands four MOSFETs can be now realized by two MOSFETs.
Further, the first and second semiconductor devices are preferably arranged in such a manner that:
the elements having opposite conduction types are paired off;
a drain of an N-type semiconductor element is fixed at a high potential, and a drain of a P-type semiconductor element is fixed at a low potential;
gates of both the N-type semiconductor element and P-type semiconductor element form a first input terminal;
the contact holes in both the N-type semiconductor element and P-type semiconductor element form a second input terminal; and
sources of both the N-type semiconductor element and P-type semiconductor element form an output terminal.
In this case, an AND or OR circuit can be realized by adequately adjusting potentials of the two inputs or impurity concentration in the channel region. Accordingly, the AND or OR circuit which conventionally demands six MOSFETs can be now realized by two MOSFETs.
Also, the first and second semiconductor devices are preferably arranged in such a manner that:
the elements having opposite conduction types are paired off;
a drain of an N-type semiconductor element is fixed at a high potential and a drain of a P-type semiconductor element is fixed at a low potential;
both a gate of the N-type semiconductor element and the contact hole in the P-type semiconductor element form a first input terminal;
both a gate of the P-type semiconductor element and the contact hole in the N-type semiconductor element form a second input terminal; and
drains of both the P-type semiconductor element and N-type semiconductor element form an output terminal.
In this case, an AND or OR circuit can be realized by adequately adjusting potentials of the two inputs or impurity concentration in the channel region. Accordingly, the AND or OR circuit which conventionally demands six MOSFETs can be now realized by two MOSFETs.
The first and second semiconductor devices are preferably arranged further in such a manner that:
the gate and the contact hole are used as separate input terminals, into which different input signals synchronized to each other are inputted, respectively. In this case, each element outputs one output signal in response to two input signals synchronized to each other based on a clock or the like. Hence, not a simple ON/OFF operation of a 1-input-1-output circuit, but an operation of a 2-input-1-output logic circuit can be realized, and therefore, the logic circuit can be composed of a fewer elements.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.